In order to generate a voltage higher or lower than a given input voltage, a power supply circuit such as a DC/DC converter (switching regulator) or the like is used. Such a power supply circuit includes an analog control type power supply circuit and a digital control type power supply circuit. In the analog control type power supply circuit, an error between an output voltage of the power supply circuit and a target value thereof is amplified by an error amplifier and a switching duty ratio is controlled based on an output from the error amplifier, thus stabilizing the output voltage with a target value. In the digital control type power supply circuit, an output voltage of the power supply circuit is converted into a digital value by an A/D converter, and a duty ratio of a switching transistor is controlled by digital signal processing.
The digital control type power supply circuit (which is also referred to as a digital control power supply circuit, hereinafter, simply as a power supply circuit) is less restricted in a control algorithm, having a high degree of freedom in design and also having an advantage in that a control scheme may be altered by software. Further, in a long-term operation, the history of various data may be maintained as digital values.
FIG. 1 is a block diagram illustrating a configuration of a digital control power supply circuit (simply referred to as a power supply circuit) reviewed by the inventors of the present disclosure.
A power supply circuit 2r includes a control circuit 10r and an output circuit 20r. The power supply circuit 2r receives an input voltage VIN from an input line 200, steps the input voltage VIN down, and supplies an output voltage VOUT to a load (not shown) connected to an output line 202.
The output circuit 20r includes a driver 204, a switching transistor M1, a synchronous rectification transistor M2, an inductor L1, and an output capacitor C1. In FIG. 1, an output circuit of a step-down (buck) DC/DC converter is illustrated. The driver 204 switches the switching transistor M1 and the synchronous rectification transistor M2 depending on a pulse signal S1 output from an output terminal OUT of the control circuit 10r. 
A feedback voltage VFB that corresponds to the output voltage \Tour is input to a feedback terminal FB of the control circuit 10r. The control circuit 10r includes an A/D converter 100, an error detector 102, a compensator 104, and a digital pulse width modulator (DPWM) 106. The A/D converter 100 converts the feedback voltage VFB into digital feedback data S2. The error detector 102 calculates error data S3 indicating a difference between the feedback data S2 and a target value DREF The compensator 104 performs PID control or the like to generate a duty command value S5 which is adjusted to make the error data S3 close to zero. The DPWM 106 receives the duty command value S5 and generates a pulse signal S1 having a corresponding duty ratio.
The present inventors have reviewed a power supply rejection ratio (PSRR) of the power supply circuit 2r of FIG. 1 and recognized the following tasks. Here, a supply voltage corresponds to the input voltage VIN of the power supply circuit 2r. 
Here, a component resulting from a voltage drop of an equivalent series resistance (ESR) of the output capacitor C1 is noted as a ripple of the output voltage VOUT The ripple VRIP at this time is expressed by Eq. (1) shown below:VRIP=ESR×VOUT×(1−D)/(L·fSW),  Eq. (1)wherein D is a switching duty ratio, fSW is a switching frequency, and L is an inductance of the inductor L1.
In the step-down DC/DC converter, the duty ratio D in a normal state is given as a ratio of the output voltage VOUT to the input voltage VIN:D=VOUT/VIN.  Eq. (2)Thus, when the input voltage VIN is changed by ±1%, the duty ratio D is also changed by ±1% and the ripple VRIP is also changed by 1%.
FIG. 2 is an operational waveform diagram of the power supply circuit 2r of FIG. 1. A case in which the A/D converter 100 samples the output voltage VOUT one time at every switching period is considered. Here, it is assumed that the output voltage VOUT is sampled at a timing when the switching transistor M1 is turned off. In this case, the output voltage VOUT is sampled at a peak of the ripple, and is fed-back while the duty ratio D is adjusted such that the peak value of the output voltage VOUT approximates a target value VREF. Supplied to the load is an average level VOUT_AVE of the output voltage VOUT, which is given by Eq. (3):VOUT_AVE=VREF−VRIP/2.  Eq. (3)That is, the average level VOUT_AVE of the output voltage VOUT decreases with the increase of the ripple VRIP. In FIG. 2, IL denotes a coil current flowing in the inductor L1.
When a PSRR given by Eq. (4) is calculated under a condition that VOUT=12 V and VRIP=25 mVpp, the PSRR becomes 60 dB, which may fall within a level that cannot be allowed depending on purposes:PSRR=20 log(VRIP/(2·VOUT))[dB].  Eq. (4)